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MCP23016
16-Bit I2CTM I/O Expander
Features
* 16-bit remote bidirectional I/O port - 16 I/O pins default to 16 inputs * Fast I2CTM bus clock frequency (0 - 400 kbits/s) * Three hardware address pins allow use of up to eight devices * High-current drive capability per I/O: 25 mA * Open-drain interrupt output on input change * Interrupt port capture register * Internal Power-On Reset (POR) * Polarity inversion register to configure the polarity of the input port data * Compatible with most microcontrollers * Available temperature range: - Industrial (I): -40C to +85C
Package Types
PDIP, SOIC, SSOP
Vss GP1.0 GP1.1 GP1.2 GP1.3 INT GP1.4 VSS CLK TP GP1.5 GP1.6 GP1.7 SCL *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GP0.7 GP0.6 GP0.5 GP0.4 GP0.3 GP0.2 GP0.1 GP0.0 VDD VSS A2 A1 A0 SDA
QFN
CMOS Technology
* Operating Supply Voltage: 2.0V to 5.5V * Low standby current
GP1.2 GP1.3 INT GP1.4 VSS CLK TP
1 2 3 4 5 6 7
Packages
* 28-pin PDIP, 300 mil; 28-pin SOIC, 300 mil * 28-pin SSOP, 209 mil; 28-pin QFN, 6x6 mm
28 27 26 2524 23 22 21 20 19 MCP23016 18 17 16 15 8 9 10 11 121314 GP1.5 GP1.6 GP1.7 SCL SDA A0 A1
GP1.1 GP1.0 Vss GP0.7 GP0.6 GP0.5 GP0.4
MCP23016
GP0.3 GP0.2 GP0.1 GP0.0 VDD VSS A2
Block Diagram
INT A0 A1 A2 SCL SDA Bus I Interface/ Protocol Handler
2CTM
Interrupt Logic
Low Pass Filter
Address Decoder I2CTM Bus Control
Serializer/ Deserializer
IARES 16 Bits I/O Port GP1.0 to GP1.7
GP0.0 to GP0.7
CLKIN TP VDD VSS
Clock Gen Power-on Reset 8-Bit
Control
Write pulse Read pulse Configuration Registers Control
(c) 2007 Microchip Technology Inc.
DS20090C-page 1
MCP23016
NOTES:
DS20090C-page 2
(c) 2007 Microchip Technology Inc.
MCP23016
1.0 DEVICE OVERVIEW
The MCP23016 device provides 16-bit, general purpose, parallel I/O expansion for I2C bus applications. This device includes high-current drive capability, low supply current and individual I/O configuration. I/O expanders provide a simple solution when additional I/Os are needed for ACPI, power switches, sensors, push buttons, LEDs and so on. The MCP23016 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the read register can be inverted with the polarity inversion register (see Section 1.7.3, "Input Polarity Registers"). All registers can be read by the system master. The open-drain interrupt output is activated when any input state differs from its corresponding input port register state. This is used to indicate to the system master that an input state has changed. The interrupt capture register captures port value at this time. The Power-on Reset sets the registers to their default values and initializes the device state machine. Three device inputs (A0 - A2) determine the I2C address and allow up to eight I/O expander devices to share the same I2C bus.
1.1
Pin Descriptions
PINOUT DESCRIPTION
PDIP, SOIC, SSOP Pin No. 9 10 2 3 4 5 7 11 12 13 21 22 23 24 25 26 27 28 14 15 6 16 17 18 1, 8, 19 20 QFN Pin No. 6 7 27 28 1 2 4 8 9 10 18 19 20 21 22 23 24 25 11 12 3 13 14 15 5, 16, 26 17 I/O/P Type I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I I I P P Buffer Type ST -- TTL TTL TTL TTL TTL ST ST ST TTL TTL TTL TTL TTL TTL TTL TTL ST ST OD ST ST ST -- -- Description
TABLE 1-1:
Pin Name
CLK TP GP1.0 GP1.1 GP1.2 GP1.3 GP1.4 GP1.5 GP1.6 GP1.7 GP0.0 GP0.1 GP0.2 GP0.3 GP0.4 GP0.5 GP0.6 GP0.7 SCL SDA INT A0 A1 A2 VSS VDD
Clock source input Test Pin (This pin must be left floating) D0 digital input/output for GP1 D1 digital input/output for GP1 D2 digital input/output for GP1 D3 digital input/output for GP1 D4 digital input/output for GP1 D5 digital input/output for GP1 D6 digital input/output for GP1 D7 digital input/output for GP1 D0 digital input/output for GP0 D1 digital input/output for GP0 D2 digital input/output for GP0 D3 digital input/output for GP0 D4 digital input/output for GP0 D5 digital input/output for GP0 D6 digital input/output for GP0 D7 digital input/output for GP0 Serial clock input Serial data I/O Interrupt output Address input 1 Address input 2 Address input 3 Ground reference for logic and I/O pins Positive supply for logic and I/O pins
(c) 2007 Microchip Technology Inc.
DS20090C-page 3
MCP23016
1.2 Power-on Reset (POR)
The on-chip POR circuit holds the chip in RESET until VDD has reached a high enough level to deactivate the POR circuit (i.e., release RESET). A maximum rise time for VDD is specified in the electrical specifications. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature) must be met to ensure proper operation. A 1 MHz (typ.) internal clock is needed for the device to function properly. The internal clock can be measured on the TP pin. Recommended REXT and CEXT values are shown in Table 1-2. Note: Set IARES = 1 to measure the clock output on TP.
TABLE 1-2:
REXT 3.9 k
RECOMMENDED VALUES
CEXT 33 pF
1.3
Power-up Timer (PWRT) 1.5
The Power-up Timer provides a 72 ms nominal timeout on power-up, keeping the device in RESET and allowing VDD to rise to an acceptable level. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See Table 2-4 for details (TPWRT, parameter 3).
I2C Bus Interface/ Protocol Handler
This block manages the functionality of the I2C bus interface and protocol handling. The MCP23016 supports the following commands:
TABLE 1-3:
1.4
Clock Generator
0h 1h 2h 3h 4h VDD 5h 6h Internal Clock CLK 7h 8h 9h Ah
COMMAND BYTE TO REGISTER RELATIONSHIP
Result Access to GP0 Access to GP1 Access to OLAT0 Access to OLAT1 Access to IPOL0 Access to IPOL1 Access to IODIR0 Access to IODIR1 Access to INTCAP0 (Read-Only) Access to INTCAP1 (Read-Only) Access to IOCON0 Access to IOCON1
The MCP23016 uses an external RC circuit to determine the internal clock speed. The user must connect R and C to the MCP23016, as shown in Figure 1-1.
Command Byte
FIGURE 1-1:
CLOCK CONFIGURATION
REXT
CEXT VSS
MCP23016
Bh
1.6
Address Decoder
The last three LSb of the 7-bit address are user-defined (see Table 1-4). Three hardware pins () define these bits.
TABLE 1-4:
0 1
DEVICE ADDRESS
0 0 A2 A1 A0
DS20090C-page 4
(c) 2007 Microchip Technology Inc.
MCP23016
1.7 Register Block
REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR The register block contains the Configuration and Port registers, as shown in Table 1-5.
TABLE 1-5:
Name
Port Registers GP0 GP1 OLAT0 OLAT1 GP0.7 GP1.7 OL0.7 OL1.7 GP0.6 GP1.6 OL0.6 OL1.6 GP0.5 GP1.5 OL0.5 OL1.5 GP0.4 GP1.4 OL0.4 OL1.4 GP0.3 GP1.3 OL0.3 OL1.3 GP0.2 GP1.2 OL0.2 OL1.2 GP0.1 GP1.1 OL0.1 OL1.1 GP0.0 GP0.0 OL0.0 OL1.0 0000 0000 0000 0000 0000 0000 0000 0000
Configuration Registers IPOL0 IPOL1 IODIR0 IODIR1 INTCAP0 INTCAP1 IOCON0 IOCON1 IGP0.7 IGP1.7 IOD0.7 IOD1.7 ICP0.7 ICP1.7 -- -- IGP0.6 IGP1.6 IOD0.6 IOD1.6 ICP0.6 ICP1.6 -- -- IGP0.5 IGP1.5 IOD0.5 IOD1.5 ICP0.5 ICP1.5 -- -- IGP0.4 IGP1.4 IOD0.4 IOD1.4 ICP0.4 ICP1.4 -- -- IGP0.3 IGP1.3 IOD0.3 IOD1.3 ICP0.3 ICP1.3 -- -- IGP0.2 IGP1.2 IOD0.2 IOD1.2 ICP0.2 ICP1.2 -- -- IGP0.1 IGP1.1 IOD0.1 IOD1.1 ICP0.1 ICP1.1 -- -- IGP0.0 IGP1.0 IOD0.0 IOD1.0 ICP0.0 ICP1.0 IARES IARES 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx xxxx xxxx ---- ---0 ---- ---0
Legend: `1' bit is set, `0' bit is cleared, x = unknown, -- = unimplemented.
(c) 2007 Microchip Technology Inc.
DS20090C-page 5
MCP23016
1.7.1 DATA PORT REGISTERS
Two registers provide access to the two GPIO ports: * GP0 (provides access to data port GP0) * GP1 (provides access to data port GP1) A read from this register provides status on pins of these ports. A write to these registers will modify the output latch registers (OLAT0, OLAT1) and data output.
REGISTER 1-1:
R/W-0 GP0.7 bit 7 bit 7-0
GP0 - GENERAL PURPOSE I/O PORT REGISTER 0
R/W-0 GP0.6 R/W-0 GP0.5 R/W-0 GP0.4 R/W-0 GP0.3 R/W-0 GP0.2 R/W-0 GP0.1 R/W-0 GP0.0 bit 0
GP0.0:GP0.7: Reflects the logic level on the pins. 1 = Logic `1' 0 = Logic `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 1-2:
R/W-0 GP1.7 bit 7 bit 7-0
GP1 - GENERAL PURPOSE I/O PORT REGISTER 1
R/W-0 GP1.6 R/W-0 GP1.5 R/W-0 GP1.4 R/W-0 GP1.3 R/W-0 GP1.2 R/W-0 GP1.1 R/W-0 GP1.0 bit 0
GP1.0:GP1.7: Reflects the logic level on the pins. 1 = Logic `1' 0 = Logic `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DS20090C-page 6
(c) 2007 Microchip Technology Inc.
MCP23016
1.7.2 OUTPUT LATCH REGISTERS
Two registers provide access to the two port output latches: * OLAT0 (provides access to the output latch for port GP0) * OLAT1 (provides access to the output latch for port GP1) A read from these registers results in a read of the latch that controls the output and not the actual port. A write to these registers updates the output latch that controls the output.
REGISTER 1-3:
R/W-0 OL0.7 bit 7 bit 7-0
OLAT0 - OUTPUT LATCH REGISTER 0
R/W-0 OL0.6 R/W-0 OL0.5 R/W-0 OL0.4 R/W-0 OL0.3 R/W-0 OL0.2 R/W-0 OL0.1 R/W-0 OL0.0 bit 0
OL0.0:O0.7: Reflects the logic level on the output latch. 1 = Logic `1' 0 = Logic `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 1-4:
R/W-0 OL1.7 bit 7 bit 7-0
OLAT1 - OUTPUT LATCH REGISTER 1
R/W-0 OL1.6 R/W-0 OL1.5 R/W-0 OL1.4 R/W-0 OL1.3 R/W-0 OL1.2 R/W-0 OL1.1 R/W-0 OL1.0 bit 0
OL1.0:O1.7: Reflects the logic level on the output latch. 1 = Logic `1' 0 = Logic `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2007 Microchip Technology Inc.
DS20090C-page 7
MCP23016
1.7.3 INPUT POLARITY REGISTERS
These registers allow the user to configure the polarity of the input port data (GP0 and GP1). If a bit in this register is set, the corresponding input port (GPn) data bit polarity will be inverted. * IPOL0 (controls the polarity of GP0) * IPOL1 (controls the polarity of GP1)
REGISTER 1-5:
R/W-0 IGP0.7 bit 7 bit 7-0
IPOL0 - INPUT POLARITY PORT REGISTER 0
R/W-0 IGP0.6 R/W-0 IGP0.5 R/W-0 IGP0.4 R/W-0 IGP0.3 R/W-0 IGP0.2 R/W-0 IGP0.1 R/W-0 IGP0.0 bit 0
IGP0.0:IGP0.7: Controls the polarity inversion for the input pins
1 = Corresponding GP0 bit is inverted 0 = Corresponding GP0 bit is not inverted Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 1-6:
R/W-0 IGP1.7 bit 7 bit 7-0
IPOL1 - INPUT POLARITY PORT REGISTER 1
R/W-0 IGP1.6 R/W-0 IGP1.6 R/W-0 IGP1.4 R/W-0 IGP1.3 R/W-0 IGP1.2 R/W-0 IGP1.1 R/W-0 IGP1.0 bit 0
IGP1.0:IGP1.7: Controls the polarity inversion for the input pins
1 = Corresponding GP1 bit is inverted 0 = Corresponding GP1 bit is not inverted Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DS20090C-page 8
(c) 2007 Microchip Technology Inc.
MCP23016
1.7.4 I/O DIRECTION REGISTERS
Two registers control the direction of data I/O: * IODIR0 (controls GP0) * IODIR1 (controls GP1) When a bit in these registers is set, the corresponding pin becomes an input. Otherwise, it becomes an output. At Power-on Reset, the device ports are configured as inputs.
REGISTER 1-7:
R/W-1 IOD0.7 bit 7 bit 7-0
IODIR0 - I/O DIRECTION REGISTER 0
R/W-1 IOD0.6 R/W-1 IOD0.5 R/W-1 IOD0.4 R/W-1 IOD0.3 R/W-1 IOD0.2 R/W-1 IOD0.1 R/W-1 IOD0.0 bit 0
IOD0.0:IO0.7: Controls the direction of data I/O
1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 1-8:
R/W-1 IOD1.7 bit 7 bit 7-0
IODIR1 - I/O DIRECTION REGISTER 1
R/W-1 IOD1.6 R/W-1 IOD1.5 R/W-1 IOD1.4 R/W-1 IOD1.3 R/W-1 IOD1.2 R/W-1 IOD1.1 R/W-1 IOD1.0 bit 0
IOD1.0:IO1.7: Controls the direction of data I/O
1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2007 Microchip Technology Inc.
DS20090C-page 9
MCP23016
1.7.5 INTERRUPT CAPTURE REGISTERS
Two registers contain the value of the port that generated the interrupt: * INTCAP0 contains the value of GP0 at time of GP0 change interrupt * INTCAP1 contains the value of GP1 at time of GP1 change interrupt These registers are `read-only' registers (A write to these registers is ignored).
REGISTER 1-9:
R-x ICP0.7 bit 7 bit 7-0
INTCAP0 - INTERRUPT CAPTURED VALUE FOR PORT REGISTER 0
R-x ICP0.6 R-x ICP0.5 R-x ICP0.4 R-x ICP0.3 R-x ICP0.2 R-x ICP0.1 R-x ICP0.0 bit 0
ICP0.0:ICP0.7: Reflects the logic level on the GP0 pins at the time of interrupt due to pin
change 1 = Logic `1' 0 = Logic `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 1-10:
R-x ICP1.7 bit 7 bit 7-0
INTCAP1 - INTERRUPT CAPTURED VALUE FOR PORT REGISTER 1
R-x ICP1.6 R-x ICP1.5 R-x ICP1.4 R-x ICP1.3 R-x ICP1.2 R-x ICP1.1 R-x ICP1.0 bit 0
ICP1.0:ICP1.7: Reflects the logic level on the GP1 pins at the time of interrupt due to pin
change 1 = Logic `1' 0 = Logic `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DS20090C-page 10
(c) 2007 Microchip Technology Inc.
MCP23016
1.7.6 I/O EXPANDER CONTROL REGISTER
* IOCON0 controls the functionality of the MCP23016. The IARES (Interrupt Activity Resolution) bit controls the sampling frequency of the GP port pins. The higher the sampling frequency, the higher the device current requirements. If this bit is `0' (default), the maximum time to detect the activity on the port is 32 ms (max.), which results in lower standby current. If this bit is `1', the maximum time to detect activity on the port is 200 sec. (max.) and results in higher standby current.
REGISTER 1-11:
U-0 -- bit 7 bit 1-7 bit 0
IOCON0 - I/0 EXPANDER CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 IARES bit 0
Unimplemented bit: Read as `0' IARES: Interrupt Activity Resolution 1 = Fast sample rate 0 = Normal sample rate Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOCON1 is a shadow register for IOCON0. Access to IOCON1 results in access to IOCON0.
(c) 2007 Microchip Technology Inc.
DS20090C-page 11
MCP23016
1.8 Serializer/Deserializer
and
1.9.1
INTERRUPT EVENT DETECTION
The Serializer/Deserializer block converts transfers data between the I2C bus and GPIO.
1.9
Interrupt Logic
The MCP23016 asserts the open-drain interrupt output (INT) low when one of the port pins changes state. Only those pins that are configured as an input can cause an interrupt. Pins defined as an output have no effect on INT. The interrupt will remain active until a read from either the port (GPn) on which the interrupt occurred or the INTCAPn register is performed. If the input returns to its previous state before a read operation, it will reset the interrupt and the INT pin output will tri-state. Each 8-bit port is read separately, so reading GP0 or INTCAP0 will not clear the interrupt generated by GP1 or INTCAP1, and vice versa. Input change activity on each port will generate an interrupt and the value of the particular port will be captured and copied into INTCAP0/INTCAP1. The INTCAPn registers are only updated when an interrupt occurs on INT. These values will stay unchanged until the user clears the interrupt by reading the port or the INTCAPn register. If the input port value changes back to normal before a user-read, the INT output will be reset. However, the INTCAP0/INTCAP1 will still contain the value of the port at the interrupt change. If the port value changes again, it will re-activate the interrupt and the new value will be captured. The first interrupt on change event following an interrupt RESET will result in a capture event. Any further change event that occurs before the interrupt is reset will not result in a capture event.
The IARES bit controls the resolution for detecting an interrupt-on-change event. If this bit is `0' (default), the maximum time for detecting a change of event is high, which results in lower standby current. If this bit is `1', it takes less time for scanning the activity on the port and results in higher standby current.
FIGURE 1-2:
READING PORTX AFTER INTERRUPT EVENT
GPx
PORT X
PORT X
INT
Port value is captured and written to INTCAPn
Read GPx or INTCAPn
Port value is captured and written to INTCAPn
DS20090C-page 12
(c) 2007 Microchip Technology Inc.
MCP23016
1.9.2 WRITING THE REGISTERS
2
FIGURE 1-3:
D7 D6 D5 D4 D3 D2 D1 D0 ACK
To write to a MCP23016 register, the Master I C device needs to follow the requirements, as illustrated in Figure 1-3. First, the device is selected by sending the slave address and setting the R/W bit to logic `0'. The command byte is sent after the address and determines which register will be written. Table 1-3 shows the relationship of the command byte and register. The MCP23016 has twelve 8-bit registers. They are configured to operate as six 16-bit register pairs, supporting the device's 16-bit port. These pairs are formed based on their functions (e.g., GP0 and GP1 are grouped together). The I2C commands apply to one register pair to provide faster access. The first data byte following a command byte is written into the register pointed to by the command byte, while the second data is written into another register in the same pair. For example, if the first byte is sent to OLAT1 (command byte 03h), the next data byte will be written into the second register of that pair, OLAT0. If the first byte is written to OLAT0 (command byte 02h), the second byte will be written to OLAT1. There is no limitation on the number of data bytes in one write transmission. Figure 1-4 shows the case of multiple byte writes in one write operation. In this case, the multiple writes are made to the same data pair. Note: The bus must remain free until after the ninth clock pulse for a minimum of 12 s (see Table 2-5 and Figure 2-4).
Data 2
WRITE TO CONFIGURATION REGISTERS (CASE 1)
P ACK D7 D6 D5 D4 D3 D2 D1 D0 Data 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
Command Byte
ACK
R/W=0
A2 A1 A0
Address
0
0
1
0
(c) 2007 Microchip Technology Inc.
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
SCL held low until data is processed
ACK
9
1
DS20090C-page 13
R/W=0 Command Byte Data 1 Data 2 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
Address
FIGURE 1-4:
DS20090C-page 14
6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL held low until data is processed Data 1 D7 D6 D5 D4 D3 D2 D1 D0 ACK Data 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 SCL held low until data is processed
0
1
0
0
A2 A1 A0
MCP23016
S
1
2
3
4
5
WRITE TO CONFIGURATION REGISTERS (CASE 2)
7
8
9
P
Address R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Command Byte
Data 1 D7 D6 D5 D4 D3 D2 D1 D0 ACK
Data 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK
FIGURE 1-5:
SDA
0
1
0
0
A2 A1 A0
SCL S 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3
1
2
3
4
5
6
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SCL held low until data is processed
Data on GP0 DATA VALID t GPV0 VALID DATA t GPV1
WRITE TO OUTPUT PORTS
(c) 2007 Microchip Technology Inc.
Data on GP1
MCP23016
1.9.3 READING THE REGISTERS FIGURE 1-6:
To read a MCP23016 register, the Master needs to follow the requirements shown in Figure 1-6. First, the device is selected by sending the slave address and setting the R/W bit to logic `0'. The command byte is sent after the address and determines which register will be read. A restart condition is generated and the device address is sent again with the R/W bit set to logic `1'. The data register defined by the command byte will be sent first, followed by the other register in the register pair. The logic for register selection is the same as explained in Write mode (Section 1.9.2, "Writing the Registers"). The falling edge of the ninth clock initiates the register read action. The SCL clock will be held low while the data is read from the register and is transferred to the I2C bus control block by the Serializer/Deserializer block. The MCP23016 holds the clock low after the falling edge of the ninth clock pulse. The configuration registers (or port control registers) are read and the value is stored. Finally, the clock is released to enable the next transmission. There is no limitation on the number of data bytes in one read transmission. Figure 1-8 shows the case of multiple byte read in one read operation. In this case, the multiple writes are made to the same data pair.
Command Byte
READ FROM CONFIGURATION REGISTER
P D7 D6 D5 D4 D3 D2 D1 D0 ACK Data from MSB or LSB of register
ACK
ACK
9
9 DS20090C-page 15 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL held low until data is processed
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
7
8
1
2
3
4
5
6
ACK
9
R/W=0
R/W=0
8
A0
A1
A2
4
0
Address
Address
3
0
2
1
1
0
(c) 2007 Microchip Technology Inc.
SDA
SCL S
0
1
0
0
A2
5
A1
6
A0
7
ACK
6
Note:
The bus must remain free until after the ninth clock pulse for a minimum of 12 s (see Table 2-5 and Figure 2-4).
Data from LSB or MSB of register
SCL held low until data is processed
7
8
1
2
3
4
5
6
7
8
9
Address R/W=0 0 ACK ACK A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK 0
Data from LSB or MSB of register
Data from MSB or LSB of register
FIGURE 1-7:
DS20090C-page 16 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL held low until data is processed
SDA
0
1
MCP23016
SCL S
1
2
Data in GP0
Read signal (Internal) for GP0 tRDd0
READ FROM INPUT PORTS (CASE 1)
Data in GP1
Read signal (Internal) for GP1 tRDd1
INT tIcd0 tIcd1
tIsd
(c) 2007 Microchip Technology Inc.
Note:
It is assumed that command byte is already set to `00'.
Address R/W=0 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 0
Data from GP0
Data from GP1
FIGURE 1-8:
SDA
0
1
0
(c) 2007 Microchip Technology Inc. 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Data from GP0 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Data from GP1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL S
1
2
3
READ FROM INPUT PORTS (CASE 2)
Note:
It is assumed that command byte is already set to 00.
MCP23016
DS20090C-page 17
MCP23016
NOTES:
DS20090C-page 18
(c) 2007 Microchip Technology Inc.
MCP23016
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................ -55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS ......................................................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +6.5V Total power dissipation (Note 1) ............................................................................................................................ 1.0 W Maximum current out of VSS pin .......................................................................................................................... 300 mA Maximum current into VDD pin ............................................................................................................................. 250 mA Input clamp current, IIK (VI < 0, or VI > VDD) ....................................................................................................... 20 mA Output clamp current, IOK (VO < 0, or VO > VDD) ................................................................................................ 20 mA Maximum output current sunk by any I/O pin......................................................................................................... 25 mA Maximum output current sourced by any I/O pin ................................................................................................... 25 mA Maximum current sunk by combined PORTS ...................................................................................................... 200 mA Maximum current sourced by combined PORTS ................................................................................................ 200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2007 Microchip Technology Inc.
DS20090C-page 19
MCP23016
2.1 DC Characteristics
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for industrial Sym VDD IDD IPD VIL Vss Vss Schmitt Trigger buffer Input High Voltage I/O ports D006 D006A D007 D008 D009 D010 D010 D011 D012 Schmitt Trigger buffer Input Leakage Current I/O ports CLK Output Low Voltage I/O Ports Output High Voltage I/O Ports VDD start voltage to ensure internal POR signal VDD rise rate to ensure internal POR signal DC Trip Point D012 VDD rise rate to ensure internal POR signal with PWRT enabled DC Current Draw Note 1: 2: 3: 4: VOH VPOR SVDD VTPOR SVDD VDD-0.7 -- 0.05 1.5 0.05 -- Vss 1.7 -- -- -- -- 1.9 -- V V V/ms Note 1 V DC Slow Ramp IOH = 3.0 mA, VDD = 4.5V VOL -- -- 0.6 V IOL = 8.5 mA, VDD = 4.5V IIL -- -- -- -- 1.0 5.0 A A Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD TTL buffer VIH 2.0 0.25 VDD + 0.8V 0.8 VDD -- -- -- -- VDD VDD VDD V V V 4.5V VDD 5.5V For entire VDD range For entire VDD range Vss -- -- -- 0.15 VDD 0.8V 0.2 VDD V V For entire VDD range 4.5V VDD 5.5V Min 2.0 -- -- Typ -- 0.4 25 Max 5.5 Units V mA A IARES = 1 IARES = 0 Conditions
TABLE 2-1:
DC CHARACTERISTICS Param No. D001 D002 D003 Characteristic Supply Voltage Standby Current Standby Current Input Low Voltage I/O ports D004 D004A D005 TTL buffer
V/ms Note 1
IPOR
--
5.0
--
A
At 5.0V (1 /Volt typical)
5:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Standby current is measured with all I/O in hi-impedance state and tied to VDD and VSS. For RC CLK, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kohm. Negative current is defined as coming out of the pin.
DS20090C-page 20
(c) 2007 Microchip Technology Inc.
MCP23016
FIGURE 2-1: RESPONSE TIME
VDD 1
TABLE 2-2:
Parameter No. 1
RESPONSE TIME
Symbol Characteristic Response Time Min 100 Typ -- Max -- Units ns Conditions Minimum time where a VDD transition from 5.0V to 0.0V to 5.0V will cause a RESET. All times less than 100 ns will be filtered.
FIGURE 2-2:
TEST POINT CLOCK TIMING
2
TTP
TABLE 2-3:
Parameter No.
TEST POINT CLOCK TIMING
Symbol FTP Characteristic TP pin Frequency TP pin CLK Period Min -- -- Typ 1.0 1.0 Max -- -- Units MHz s Conditions Measured at TP pin, IARES = `1'. Measured at TP pin, IARES = `1'.
2
TTP
Data in "Typ" column is at 5V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 2-4:
Parameter No. 3
POWER-UP TIMER REQUIREMENTS
Symbol TPWRT Characteristic Power-up Timer Period Min -- Typ 72 Max -- Units ms Conditions
Data in "Typ" column is at 5V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2007 Microchip Technology Inc.
DS20090C-page 21
MCP23016
FIGURE 2-3: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition
STOP Condition
TABLE 2-5:
Param No. 90 91
I2C BUS START/STOP BITS REQUIREMENTS
Symbol TSU:STA THD:STA Characteristic START condition Setup time START condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Ty Max Units p -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated START condition (Note 1) After this period, the first clock pulse is generated (Note 1)
92 93 Note 1:
TSU:STO THD:STO
STOP condition Setup time STOP condition Hold time
These parameters are characterized but not tested.
DS20090C-page 22
(c) 2007 Microchip Technology Inc.
MCP23016
FIGURE 2-4: I2C BUS DATA TIMING
103 SCL 100 101 90 91 SDA In 110 109 SDA Out 109 106 111 107 92 102
(c) 2007 Microchip Technology Inc.
DS20090C-page 23
MCP23016
TABLE 2-5:
Param No. 100 101 102
I2C BUS DATA REQUIREMENTS
Characteristic Clock High Time Clock Low Time 100 kHz mode 400 kHz mode TLOW TR 100 kHz mode 400 kHz mode SDA and SCL Rise 100 kHz mode Time 400 kHz mode SDA and SCL Fall Time START Condition Setup Time START Condition Hold Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode CB Bus Capacitive Loading Clock wait time after ninth pulse 100 kHz mode 400 kHz mode Min 4.0 0.6 4.7 1.3 -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- 12 s 12 s Max -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 -- -- Units s s s s ns ns ns ns s s s s ns s ns ns s s ns ns s s pF s s Time the bus must remain free after the ninth clock pulse before a new transmission can start. Time the bus must be free before a new transmission can start (Note 1) (Note 1) (Note 2) (Note 1) (Note 1) (Note 3) (Note 1) CB is specified to be from 10 - 400 pF (Note 1) CB is specified to be from 10 - 400 pF Only relevant for repeated START condition (Note 1) After this period, the first clock pulse is generated (Note 1) (Note 1) (Note 1) Conditions (Note 1)
Symbol THIGH
103
TF
90 91
TSU:STA THD:STA
106 107 92 109 110
THD:DAT TSU:DAT TSU:STO TAA TBUF
111
TWAIT
Note 1: 2: 3:
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
DS20090C-page 24
(c) 2007 Microchip Technology Inc.
MCP23016
TABLE 2-7:
Param No.
GP0 AND GP1 TIMING REQUIREMENTS
Characteristic GP0 output data valid time GP1 output data valid time GP0 data read delay time GP1 data read delay time GP0 Interrupt set delay time GP1 Interrupt set delay time GP0 Interrupt clear delay time (for read) GP1 Interrupt clear delay time (for read) Min -- -- -- -- -- -- -- -- -- Typ. 40 50 40 50 -- -- -- -- 100 Max -- -- -- -- 200 32 200 32 -- Units s s s s s ms s ms s IARES = 1, TP = 1 MHz IARES = 0, TP = 1 MHz IARES = 1, TP = 1 MHz IARES = 0, TP = 1 MHz TP = 1 MHz Conditions TP = 1 MHz
Symbol tGPV0 tGPV1 tRDd0 tRDd1 tISD0 tISD1 tLCD0
tLCD1
--
100
--
s
Note 1:
These parameters are characterized but not tested.
(c) 2007 Microchip Technology Inc.
DS20090C-page 25
Address R/W=0 A2 A1 ACK A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 0 0
Data from LSB or MSB of register
Data from MSB or LSB of register
FIGURE 2-5:
DS20090C-page 26 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL held low until data is processed
SDA
0
1
MCP23016
SCL S
1
2
Data in GP0
GP0 AND GP1 PORT TIMINGS
Read signal(Internal) for GP0 tRDd0
Data in GP1
Read signal(Internal) for GP1 tRDd1
INT tIcd0 tIcd1
tIsd
(c) 2007 Microchip Technology Inc.
Note:
It is assumed that command byte is already set to `00'.
MCP23016
3.0
3.1
PACKAGE INFORMATION
Package Marking Information
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example:
MCP23016-I/SP e3 0717017
28-Lead SOIC
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example:
MCP23016-I/SO e3 0710017
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example:
MCP23016 -I/SS e3 0720017
28-Lead QFN
Example:
XXXXXXXX XXXXXXXX YYWWNNN
MCP23016 -I/ML e3 0710017
Legend: XX...X Y YY WW NNN *
e3
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this package.
)
e3
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2007 Microchip Technology Inc.
DS20090C-page 27
MCP23016
28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1 E1
123 D E A A2 L A1 b1 b e eB c
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width N e A A2 A1 E E1 D L c b1 b - .120 .015 .290 .240 1.345 .110 .008 .040 .014 MIN
INCHES NOM 28 .100 BSC - .135 - .310 .285 1.365 .130 .010 .050 .018 .200 .150 - .335 .295 1.400 .150 .015 .070 .022 MAX
Overall Row Spacing eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M.
(c) 2007 Microchip Technology Inc.
DS20090C-page 28
MCP23016
28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 123 b e

h h c
A
A2
L A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.18 0.31 5 5 0.25 0.40 - 2.05 0.10 MIN
MILLMETERS NOM 28 1.27 BSC - - - 10.30 BSC 7.50 BSC 17.90 BSC - - 1.40 REF - - - - - 8 0.33 0.51 15 0.75 1.27 2.65 - 0.30 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B
(c) 2007 Microchip Technology Inc.
DS20090C-page 29
MCP23016
28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
12 NOTE 1
b e
c A A2 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 9.90 0.55 MIN MILLIMETERS NOM 28 0.65 BSC - 1.75 - 7.80 5.30 10.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 10.50 0.95 MAX
A1
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-073B
DS20090C-page 30
(c) 2007 Microchip Technology Inc.
MCP23016
28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D2
EXPOSED PAD
e E E2 2 1 N NOTE 1 TOP VIEW BOTTOM VIEW 2 1 N L K
b
A
A3
A1
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 3.65 0.23 0.50 0.20 3.65 0.80 0.00 MIN MILLIMETERS NOM 28 0.65 BSC 0.90 0.02 0.20 REF 6.00 BSC 3.70 6.00 BSC 3.70 0.30 0.55 - 4.20 0.35 0.70 - 4.20 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-105B
(c) 2007 Microchip Technology Inc.
DS20090C-page 31
MCP23016
NOTES:
DS20090C-page 32
(c) 2007 Microchip Technology Inc.
MCP23016
APPENDIX A: REVISION HISTORY
Revision A (December 2002)
Original data sheet for MCP23016 device.
Revision B (September 2003)
1. 2. Addition of Output Low Voltage section to Table 2-1 in Electrical Characteristics. Addition of Output High Voltage section to Table 2-1 in Electrical Characteristics.
Revision C (January 2007)
This revision includes updates to the packaging diagrams.
(c) 2007 Microchip Technology Inc.
DS20090C-page 33
MCP23016
NOTES:
DS20090C-page 34
(c) 2007 Microchip Technology Inc.
MCP23016
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package
Examples:
a) a) a) a) DSTEMP-I/P: DSTEMP-I/SO: DSTEMP-I/SS: DSTEMP-I/ML: Industrial Temperature, PDIP package. Industrial Temperature, SOIC package. Industrial Temperature, SOIC package. Industrial Temperature, QFN package.
Device: Temperature Range: Package:
DSTEMP: 16-Bit I2C I/O Expander I = -40C to +85C
SP SO SS ML
= = = =
Plastic DIP (300 mil Body), 28-lead Plastic SOIC, Wide (300 mil Body), 28-lead Plastic SOIC, (209 mil, 5.30mm), 28-lead Plastic Quad, Flat No Leads (QFN), 28-lead
(c) 2007 Microchip Technology Inc.
DS20090C-page 35
MCP23016
NOTES:
DS20090C-page 36
(c) 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2007 Microchip Technology Inc.
DS20090C-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS20090C-page 38
(c) 2007 Microchip Technology Inc.

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